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28C16AT-25I/P PDF预览

28C16AT-25I/P

更新时间: 2024-11-27 03:55:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
10页 126K
描述
16K (2K x 8) CMOS EEPROM

28C16AT-25I/P 数据手册

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Obsolete Device  
28C16A  
16K (2K x 8) CMOS EEPROM  
FEATURES  
PACKAGE TYPES  
A7  
A6  
• 1  
2
24 Vcc  
23 A8  
• Fast Read Access Time—150 ns  
• CMOS Technology for Low Power Dissipation  
- 30 mA Active  
A6  
A5  
A4  
A3  
A2  
A1 10  
A0 11  
NC 12  
I/O0 13  
5
6
7
8
9
29 A8  
28 A9  
A5  
3
22 A9  
A4  
4
21 WE  
20 OE  
19 A10  
18 CE  
17 I/O7  
16 I/O6  
15 I/O5  
14 I/O4  
13 I/O3  
27 NC  
26 NC  
25 OE  
24 A10  
23 CE  
22 I/O7  
21 I/O6  
A3  
5
- 100 µA Standby  
A2  
6
• Fast Byte Write Time—200 µs or 1 ms  
• Data Retention >200 years  
• High Endurance - Minimum 104 Erase/Write Cycles  
• Automatic Write Operation  
- Internal Control Timer  
A1  
7
A0  
8
I/O0  
I/O1  
I/O2  
9
10  
11  
VSS 12  
- Auto-Clear Before Write Operation  
- On-Chip Address and Data Latches  
• Data polling  
• Pin 1 indicator on PLCC on top of package  
BLOCK DIAGRAM  
• Chip Clear Operation  
• Enhanced Data Protection  
- VCC Detector  
- Pulse Filter  
- Write Inhibit  
• Electronic Signature for Device Identification  
• 5-Volt-Only Operation  
• Organized 2Kx8 JEDEC Standard Pinout  
• 24-pin Dual-In-Line Package  
• 32-pin PLCC Package  
I/O0  
I/O7  
V
SS  
Data Protection  
Circuitry  
Chip Enable/  
Output Enable  
Control Logic  
VCC  
CE  
OE  
Input/Output  
WE  
Auto Erase/Write  
Timing  
Data  
Poll  
Buffers  
Program Voltage  
Generation  
• Available for Extended Temperature Ranges:  
- Commercial: 0°C to +70°C  
- Industrial: -40°C to +85°C  
A0  
Y
Y Gating  
Decoder  
L
a
t
c
h
e
s
DESCRIPTION  
16K bit  
Cell Matrix  
X
Decoder  
The Microchip Technology Inc. 28C16A is a CMOS 16K  
non-volatile electrically Erasable PROM. The 28C16A  
is accessed like a static RAM for the read or write  
cycles without the need of external components. Dur-  
ing a “byte write”, the address and data are latched  
internally, freeing the microprocessor address and data  
bus for other operations. Following the initiation of  
write cycle, the device will go to a busy state and auto-  
matically clear and write the latched data using an  
internal control timer. To determine when a write cycle  
is complete, the 28C16A uses Data polling. Data poll-  
ing allows the user to read the location last written to  
when the write operation is complete. CMOS design  
and processing enables this part to be used in systems  
where reduced power consumption and reliability are  
required. A complete family of packages is offered to  
provide the utmost flexibility in applications.  
A10  
2004 Microchip Technology Inc.  
DS11125J-page 1  

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