28C16A
16K (2K x 8) CMOS EEPROM
FEATURES
PACKAGE TYPES
A7
A6
• 1
2
24 Vcc
23 A8
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
A6
A5
A4
A3
A2
A1 10
A0 11
NC 12
I/O0 13
5
6
7
8
9
29 A8
28 A9
A5
3
22 A9
A4
4
21 WE
20 OE
19 A10
18 CE
17 I/O7
16 I/O6
15 I/O5
14 I/O4
13 I/O3
27 NC
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
A3
5
- 100 µA Standby
A2
6
• Fast Byte Write Time—200 µs or 1 ms
• Data Retention >200 years
A1
7
A0
8
4
I/O0
I/O1
I/O2
9
• High Endurance - Minimum 10 Erase/Write Cycles
10
11
• Automatic Write Operation
- Internal Control Timer
VSS 12
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data polling
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
• Pin 1 indicator on PLCC on top of package
OE
NC
A9
1
2
3
4
5
6
7
28 A10
27
CE
26 I/07
25 I/06
24 I/05
23 I/04
22 I/03
A8
NC
WE
Vcc
- Pulse Filter
- Write Inhibit
NC
NC
8
9
21 Vss
20 I/02
19 I/01
18 I/00
17 A0
16 A1
15 A2
A7 10
A6 11
A5 12
A4 13
A3 14
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 2Kx8 JEDEC Standard Pinout
• 24-pin Dual-In-Line Package
• 32-pin PLCC Package
• 28-pin Thin Small Outline Package (TSOP)
8x20mm
• 28-pin Very Small Outline Package (VSOP)
8x13.4mm
OE
NC
A9
A8
NC
WE
22
23
24
25
26
27
A10
CE
21
20
19
18
17
16
15
14
13
12
11
10
9
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
28
1
VCC
NC
2
3
4
5
6
7
NC
A7
A6
A5
A4
A3
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
A1
A2
8
BLOCK DIAGRAM
DESCRIPTION
I/O0
I/O7
The Microchip Technology Inc. 28C16A is a CMOS 16K
non-volatile electrically Erasable PROM. The 28C16A
is accessed like a static RAM for the read or write
cycles without the need of external components. Dur-
ing a “byte write”, the address and data are latched
internally, freeing the microprocessor address and data
bus for other operations. Following the initiation of
write cycle, the device will go to a busy state and auto-
matically clear and write the latched data using an
internal control timer. To determine when a write cycle
is complete, the 28C16A uses Data polling. Data poll-
ing allows the user to read the location last written to
when the write operation is complete. CMOS design
and processing enables this part to be used in systems
where reduced power consumption and reliability are
required. A complete family of packages is offered to
provide the utmost flexibility in applications.
VSS
Data Protection
VCC
Circuitry
Chip Enable/
Output Enable
Control Logic
CE
OE
Input/Output
Buffers
WE
Auto Erase/Write
Timing
Data
Poll
Program Voltage
Generation
A0
Y
Y Gating
Decoder
L
a
t
c
h
e
s
16K bit
X
Decoder
Cell Matrix
A10
1996 Microchip Technology Inc.
DS11125G-page 1
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