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25C040T-I/P PDF预览

25C040T-I/P

更新时间: 2024-11-20 02:56:03
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
22页 402K
描述
4K SPI ⑩ Bus Serial EEPROM

25C040T-I/P 数据手册

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Not recommended for new designs –  
Please use 25AA040A or 25LC040A.  
25AA040/25LC040/25C040  
4K SPI Bus Serial EEPROM  
Communication to the device can be paused via the  
hold pin (HOLD). While the device is paused, transi-  
tions on its inputs will be ignored, with the exception of  
Chip Select, allowing the host to service higher priority  
interrupts. Also, write operations to the device can be  
disabled via the write-protect pin (WP).  
Device Selection Table  
Part  
Number  
VCC  
Range  
Max. Clock  
Frequency  
Temp.  
Ranges  
25AA040  
25LC040  
25C040  
1.8-5.5V  
2.5-5.5V  
4.5-5.5V  
1 MHz  
2 MHz  
3 MHz  
I
I
Package Types  
I,E  
PDIP  
CS  
1
8
VCC  
Features:  
SO  
2
3
7
6
HOLD  
SCK  
• Low-power CMOS technology:  
- Write current: 3 mA, typical  
- Read current: 500 μA, typical  
- Standby current: 500 nA, typical  
• 512 x 8-bit organization  
• 16 byte page  
WP  
VSS  
4
5
SI  
SOIC  
CS  
1
8
VCC  
SO  
2
3
7
6
HOLD  
SCK  
• Write cycle time: 5 ms max.  
• Self-timed Erase and Write cycles  
• Block write protection:  
WP  
VSS  
4
5
SI  
TSSOP  
- Protect none, 1/4, 1/2 or all of array  
• Built-in write protection:  
- Power on/off data protection circuitry  
- Write enable latch  
1
2
8
HOLD  
VCC  
SCK  
SI  
7
6
5
3
4
CS  
SO  
VSS  
WP  
- Write-protect pin  
• Sequential read  
• High reliability:  
Block Diagram  
- Endurance: 1M cycles  
STATUS  
Register  
HV Generator  
- Data retention: > 200 years  
- ESD protection: > 4000V  
• 8-pin PDIP, SOIC and TSSOP packages  
Temperature ranges supported:  
- Industrial (I):  
- Automotive (E) (25C040):  
-40°C to +85°C  
EEPROM  
Array  
Memory  
Control  
Logic  
-40°C to +125°C  
I/O Control  
Logic  
XDEC  
Description:  
Page  
Latches  
The Microchip Technology Inc. 25AA040/25LC040/  
25C040 (25XX040*) is a 4 Kbit serial Electrically  
Erasable PROM. The memory is accessed via a simple  
Serial Peripheral Interface (SPI) compatible serial bus.  
The bus signals required are a clock input (SCK) plus  
separate data in (SI) and data out (SO) lines. Access to  
the device is controlled through a Chip Select (CS)  
input.  
SI  
SO  
Y Decoder  
CS  
SCK  
Sense Amp.  
R/W Control  
HOLD  
WP  
VCC  
VSS  
*25XX040 is used in this document as a generic part number  
for the 25AA040/25LC040/25C040 devices.  
© 2006 Microchip Technology Inc.  
DS21204E-page 1  

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