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24AA64XT-E/MNY PDF预览

24AA64XT-E/MNY

更新时间: 2024-11-01 06:26:03
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
40页 862K
描述
64K I2C™ Serial EEPROM

24AA64XT-E/MNY 数据手册

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24AA64/24LC64/24FC64  
64K I2CSerial EEPROM  
• Pb-Free and RoHS Compliant  
Temperature Ranges:  
Device Selection Table  
Part  
VCC  
Max. Clock  
Temp.  
Ranges  
- Industrial (I): -40°C to +85°C  
Number  
Range  
Frequency  
- Automotive (E): -40°C to +125°C  
24AA64  
24LC64  
24FC64  
1.7-5.5  
2.5-5.5  
1.7-5.5  
400 kHz(1)  
400 kHz  
1 MHz(2)  
I
I, E  
I
Description:  
The Microchip Technology Inc. 24AA64/24LC64/  
24FC64 (24XX64*) is a 64 Kbit Electrically Erasable  
PROM. The device is organized as a single block of  
8K x 8-bit memory with a 2-wire serial interface. Low-  
voltage design permits operation down to 1.7V, with  
standby and active currents of only 1 A and 3 mA,  
respectively. It has been developed for advanced, low-  
power applications such as personal communications  
or data acquisition. The 24XX64 also has a page write  
capability for up to 32 bytes of data. Functional  
address lines allow up to eight devices on the same  
bus, for up to 512 Kbits address space. The 24XX64 is  
available in the standard 8-pin PDIP, surface mount  
SOIC, SOIJ, TSSOP, DFN, TDFN and MSOP  
Note 1: 100 kHz for VCC <2.5V  
2: 400 kHz for VCC <2.5V  
Features:  
• Single-Supply with Operation down to 1.7V for  
24AA64/24FC64 devices, 2.5V for 24LC64  
devices  
• Low-Power CMOS Technology:  
- Active current 3 mA, max.  
- Standby current 1 A, max.  
• 2-Wire Serial Interface, I2C™ Compatible  
packages. The 24XX64 is also available in the 5-lead  
SOT-23, and Chip Scale packages.  
• Packages with 3 Address Pins are cascadable up  
to 8 devices  
Block Diagram  
• Schmitt Trigger Inputs for Noise Suppression  
• Output Slope Control to Eliminate Ground Bounce  
• 100 kHz and 400 kHz Clock Compatibility  
• 1 MHz Clock for FC versions  
HV  
A0 A1 A2WP  
Generator  
• Page Write Time 5 ms, max.  
I/O  
Control  
Logic  
Memory  
Control  
Logic  
EEPROM  
Array  
• Self-timed Erase/Write Cycle  
XDEC  
• 32-Byte Page Write Buffer  
Page  
Latches  
• Hardware Write-protect  
• ESD Protection > 4,000V  
I/O  
SCL  
• More than 1 Million Erase/Write Cycles  
• Data Retention > 200 Years  
YDEC  
SDA  
• Factory Programming Available  
• Packages include 8-lead PDIP, SOIC, SOIJ,  
TSSOP, X-Rotated TSSOP, MSOP, DFN, TDFN,  
5-lead SOT-23 or Chip Scale  
VCC  
VSS  
Sense Amp.  
R/W Control  
Package Types  
CS (Chip Scale)(1)  
PDIP/MSOP/SOIC/SOIJ/TSSOP  
DFN/TDFN  
SOT-23  
X-Rotated TSSOP  
SCL  
VSS  
WP  
5
4
1
2
VCC  
A0  
1
VCC  
WP  
8
7
VSS  
1
4
2
5
A0  
1
8
VCC  
(X/ST)  
3
WP  
SCL  
2
3
4
A1  
A1  
A2  
2
3
4
7
6
5
WP  
1
2
3
4
8
7
6
5
WP  
SCL  
SDA  
SDA  
SCL  
SDA  
6
5
A2  
VSS  
V
CC  
A0  
A1  
SCL  
SDA  
VSS  
VCC  
3
(Top Down View,  
Balls Not Visible)  
SDA  
A2  
VSS  
Note 1: Available in I-temp, “AA” only.  
* 24XX64 is used in this document as a generic part number for the 24AA64/24LC64/24FC64 devices.  
2010 Microchip Technology Inc.  
DS21189R-page 1  

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