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23S05E PDF预览

23S05E

更新时间: 2024-10-15 14:58:23
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
9页 222K
描述
3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible

23S05E 数据手册

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IDT23S05E  
3.3V ZERO DELAY CLOCK  
BUFFER, SPREAD SPECTRUM  
COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 200MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT23S05E is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 200MHz.  
• Output Skew < 250ps  
The IDT23S05E is an 8-pin version of the IDT23S09E. IDT23S05E  
accepts one reference input, and drives out five low skew clocks. The -1H  
version of this device operates up to 200MHz frequency and has a higher  
drive than the -1 device. All parts have on-chip PLLs which lock to an input  
clockontheREFpin. ThePLLfeedbackison-chipandisobtainedfromthe  
CLKOUT pad. In the absence of an input clock, the IDT23S05E enters  
• Low jitter <200 ps cycle-to-cycle  
• IDT23S05E-1 for Standard Drive  
• IDT23S05E-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Spread spectrum compatible  
• Available in SOIC package  
power down. In this mode, the device will draw less than 12µA for  
CommercialTemperaturerangeandlessthan2AforIndustrialtempera-  
ture range, the outputs are tri-stated, and the PLL is not running, resulting  
in a significant reduction of power.  
The IDT23S05E is characterized for both Industrial and Commercial  
operation.  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2010  
1
.  
DSC - 6398/7  

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