Datasheet > 2305A

2305A

更新时间： 2024-11-25 14:57:19

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
8页	266K
描述
3.3V Zero Delay Clock Buffer

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数据手册

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2305A 数据手册

IDT2305A

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT2305A

3.3V ZERO DELAY CLOCK

BUFFER

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five outputs

• Zero Input-Output Delay

The IDT2305A is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

• Output Skew < 250ps

The IDT2305A is an 8-pin version of the IDT2309A. IDT2305A accepts

one reference input, and drives out five low skew clocks. The -1H version

ofthisdeviceoperatesupto133MHzfrequencyandhasahigherdrivethan

the -1 device. All parts have on-chip PLLs which lock to an input clock on

theREFpin.ThePLLfeedbackison-chipandisobtainedfromtheCLKOUT

pad. In the absence of an input clock, the IDT2305A enters power down.

• Low jitter <200 ps cycle-to-cycle

• IDT2305A-1 for Standard Drive

• IDT2305A-1H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Power down mode

• Available in SOIC package

Inthismode,thedevicewilldrawlessthan12μAforCommercialTempera-

turerangeandlessthan 25μAforIndustrialtemperaturerange, theoutputs

aretri-stated,andthePLLisnotrunning,resultinginasignificantreduction

of power.

The IDT2305A is characterized for both Industrial and Commercial

operation.

FUNCTIONALBLOCKDIAGRAM

CLKOUT

CLK1

PLL

Control

Logic

REF

CLK2

CLK3

CLK4

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

AUGUST 2012

2012 Integrated Device Technology, Inc.

DSC 6586/4

12 3 4 5 6 7 8

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2305B-1DCI	IDT	获取价格	3.3V ZERO DELAY CLOCK BUFFER
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2305B-1HDCG	IDT	获取价格	3.3V ZERO DELAY CLOCK BUFFER
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