Datasheet > 2305

2305

更新时间： 2024-11-22 14:57:35

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
13页	312K
描述
3.3V Zero Delay Low Skew Buffer

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数据手册

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2305 数据手册

IDT2305

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT2305

3.3V ZERO DELAY

CLOCK BUFFER

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five outputs

• Zero Input-Output Delay

The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

• Output Skew < 250ps

The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one

referenceinput,anddrivesoutfivelowskewclocks.The-1Hversionofthis

device operates, up to 133MHz frequency and has a higher drive than the

-1 device. All parts have on-chip PLLs which lock to an input clock on the

REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT

pad. In the absence of an input clock, the IDT2305 enters power down. In

• Low jitter <200 ps cycle-to-cycle

• IDT2305-1 for Standard Drive

• IDT2305-1H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Power down mode

• Available in SOIC/TSSOP packages

this mode, the device will draw less than 25µA, the outputs are tri-stated,

and the PLL is not running, resulting in a significant reduction of power.

The IDT2305 is characterized for both Industrial and Commercial

operation.

FUNCTIONALBLOCKDIAGRAM

CLKOUT

CLK1

PLL

Control

Logic

REF

CLK2

CLK3

CLK4

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

AUGUST 2012

2012 Integrated Device Technology, Inc.

DSC 5174/8

12 3 4 5 6 7...13

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