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16CV8J-25

更新时间： 2024-09-24 05:57:31
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CMOS Programmable Electrically Erasable Logic Device

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16CV8J-25 数据手册

 浏览型号16CV8J-25的Datasheet PDF文件第2页浏览型号16CV8J-25的Datasheet PDF文件第3页浏览型号16CV8J-25的Datasheet PDF文件第4页浏览型号16CV8J-25的Datasheet PDF文件第5页浏览型号16CV8J-25的Datasheet PDF文件第6页浏览型号16CV8J-25的Datasheet PDF文件第7页 
Commercial  
PEEL™ 16CV8 -25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
•
•
•
Compatible with Popular 16V8 Devices  
•
•
Multiple Speed, Power Options  
- Speeds range 25ns  
- Power as low as 37mA @ 25mHZ  
Development / Programmer Support  
- Third party software and programmers  
- ICT PLACE Development Software  
- Automatic programmer translation and JEDEC file translation  
software available for the most popular PAL devices  
- 16V8 socket and function compatible  
- Programs with standard 16V8 JEDEC file  
- 20-pin DIP, SOIC, TSSOP, and PLCC  
CMOS Electrically Erasable Technology  
- Superior factory testing  
- Reprogrammable in plastic package  
- Reduces retrofit and development costs  
Application Versatility  
- Replaces random logic  
- Super sets standard 20-pin PLDs (PALs)  
General Description  
The PEELTM 16CV8 is a Programmable Electrically Erasable Logic  
(PEEL) device providing an attractive alternative to ordinary PLDs. The  
PEELTM 16CV8 offers the performance, flexibility, ease of design and  
production practicality needed by logic designers today.  
The PEELTM 16CV8 architecture allows it to replace over standard 20-  
pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. ICT’s PEELTM 16CV8  
can be programmed with existing 16CV8 JEDEC file. Some program-  
mers also allow the PEELTM 16CV8 to be programmed directly from  
PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional development  
The PEELTM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP  
packages (see Figure 1) with 25ns speed and power consumption as  
low as 37mA. EE-Reprogrammability provides the convenience of  
instant reprogramming for development and reusable production inven-  
tory minimizing the impact of programming changes or errors. EE-  
Reprogrammability also improves factory testability, thus assuring the  
highest quality possible.  
and programming support for the PEELTM16CV8 is provided by popular  
third-party programmers and development software. ICT also offers free  
PLACE development software.  
Figure 1 - Pin Configuration  
Figure 2 - Block Diagram  
I/CLK1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
I/CLK1  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
I
I
I
I
I
I
I
I
I
CLK  
I
/ CLK  
I
PEEL  
"AND"  
ARRAY  
I
I
I
I/ O  
MACRO  
CELL  
I
I
I/ O  
I/ O  
I/ O  
I/ O  
I/ O  
I/ O  
I/ O  
64 TERMS  
X
32 INPUTS  
GND  
GND  
I
DIP  
TSSOP  
I/ OE  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
I/CLK1  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
I
I
I
I
I
I
I
I
3
2
1
19  
20  
I
I
I
I
I
I/O  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
8
18  
17  
16  
15  
14  
9 10 11 12 13  
10  
GND  
PLCC-J  
SOIC  
1
04-02-004I  
1234567...10

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