Datasheet > 1442_05

1442_05

更新时间： 2024-09-24 06:16:15

品牌	Logo	应用领域
威世 - VISHAY		/
页数	文件大小	规格书
3页	173K
描述
Bulk Metal® Foil Technology Dual-In-Line Hermetic Resistor Networks

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1442_05 数据手册

1442, 1445, 1446

Vishay Foil Resistors

Bulk Metal^®Foil Technology

Dual-In-Line Hermetic Resistor Networks

Vishay Model 1442, 1445 and 1446 networks incorporate all the

performance features of Vishay Bulk Metal^®Foil technology.

The 8, 14 and 16 pin side brazed DIPs are a ceramic package.

Ceramichastheadvantageofelectricalisolationontheunderside,

and,inDIPform,afavorablepinarrangementwhentwonetworks

are to be placed side by side and connected together.

Review data sheet “7 Technical Reasons to Specify Bulk

Metal Foil Resistor Networks.”

Networks are built to your requirements. Send your schematic

and electrical requirements to the Applications Engineering

Department. (See data sheet “Network Worksheet.”) A unique

part number will be assigned which defines all aspects of your

network.

Product may not

be to scale

FIGURE 1 - PACKAGE SIZES AND CHARACTERISTICS

0.008 to 0.016

(0.20 to 0.41)

0.200

(5.08)

MAXIMUM

0.300 ±0.010

(7.62 ±0.25)

0.015 to 0.022

(0.38 to 0.56)

NO. 1 LEAD

NOTE:

0.100

(2.54)

TYPICAL

1. These networks utilize Vishay Bulk Metal^®Foil resistor chips V5X5 and V15X5 or VTF15X5 Thin Film chips.

2. The V5X5 and V15X5 chips have maximum resistance values of 10K and 33K respectively in Bulk Metal^®Foil and 500K in

VTF15X5 Thin Film chips.

3. The V5X5 and V15X5 chip(s) can be intermixed in a package.

MAXIMUM DIMENSIONS in Inches (mm)

CHIP CAPACITY

VISHAY

MODEL

NO. OF

PINS

MAXIMUM POWER RATING

V5X5 V15X5 (WATTS) @ +70°C

1442

1445

1446

0.520 ±0.020

(13.21 ±0.51)

0.295 ±0.010

(7.49 ±0.025)

0.054

(1.37)

0.125 minimum

(3.18)

0.4

1.2

1.4

0.740 ±0.045 0.270 +0.035/–0.030

(18.80 ±1.14) (6.86 +0.89/–0.76)

0.046

(1.17)

0.135 +0.015/–0.010

(3.43 +0.38/–0.25)

0.780 ±0.030

(19.81 ±0.76)

0.290 ±0.008

(7.37 ±0.20)

0.040 to 0.070 0.135 +0.015/–0.010

(1.01 to 1.78) (3.43 +0.38/–0.25)

FIGURE 2 - SAMPLE CIRCUIT DESIGN AND CHIP LAYOUT

NOTE:

Usable area is represented by

the dotted lines— a rectangle

0.150 Inches x 0.200 Inches.

Illustrations not to scale. Chips

shown undersize for clarity.

Drawing view is from the top

looking down into the package.

SALES

• ISRAEL: foilsales.israel@vishay.com

• ASIA/JAPAN: foilsales.asia@vishay.com • UK/HOLLAND/SCANDINAVIA: foilsales.eunorth@vishay.com • GERMANY/CZECH REPUBLIC/AUSTRIA: foilsales.eucentral@vishay.com

• FRANCE/SWITZERLAND/SOUTHERN EUROPE: foilsales.eusouth@vishay.com

• AMERICAS: foilsales.usa@vishay.com

For technical questions in the Americas, contact foilsupport1@vishay.com

For technical questions in Asia/Japan/Europe/Africa/Israel, contact foilsupport2@vishay.com

www.vishay.com

126

Document Number: 63032

Revision 08-Mar-05

12 3

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