Datasheet > 11C91DC

11C91DC

更新时间： 2024-01-04 22:43:13

品牌	Logo	应用领域
其他 - ETC		预分频器逻辑集成电路时钟
页数	文件大小	规格书
10页	158K
描述
Prescaler/Frequency Divider

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技术参数
数据手册

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11C91DC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	DIP, DIP16,.3
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.92	JESD-30 代码：	R-XDIP-T16
JESD-609代码：	e0	逻辑集成电路类型：	PRESCALER
湿度敏感等级：	2A	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	250
认证状态：	Not Qualified	筛选级别：	MIL-STD-883 Class C
子类别：	Prescaler/Multivibrators	表面贴装：	NO
技术：	ECL	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	Base Number Matches：	1

11C91DC 数据手册

Not Intended For New Designs

August 1992

11C90/11C91

650 MHz Prescalers

General Description

The 11C90 and 11C91 are high-speed prescalers designed

specifically for communication and instrumentation applica-

tions. All discussions and examples in this data sheet are

applicable to the 11C91 as well as the 11C90.

also allows power consumption to be reduced by leaving

the separate V pin open if the TTL output is not used.

To facilitate capacitive coupling of the clock signal, a 400X

resistor (V

) is connected internally to the V reference.

REF BB

The 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6,

both over a frequency range from DC to typically 650 MHz.

The division ratio is controlled by the Mode Control. The

divide-by-10 or -11 capability allows the use of pulse swal-

lowing techniques to control high-speed counting modulos

by lower-speed circuits. The 11C90 may be used with either

ECL or TTL power supplies.

Connecting this resistor to the Clock Pulse input (CP) auto-

matically centers the input about the switching threshold.

Maximum frequency operation is achieved with a 50% duty

cycle.

Each of the Mode Control inputs is connected to an internal

2 kX resistor with the other end uncommitted (RM and

RM ). An M input can be driven from a TTL circuit operating

In addition to the ECL outputs Q and Q, the 11C90 contains

an ECL-to-TTL converter and a TTL output. The TTL output

from the same V by connecting the free end of the asso-

ciated 2 kX resistor to V

. When an M input is driven

CCA

operates from the same V and V levels as the counter,

CC EE

from the ECL circuit, the 2 kX resistor can be left open or, if

but a separate pin is used for the TTL circuit V . This mini-

mizes noise coupling when the TTL output switches and

required, can be connected to V

resistor.

to act as a pull-down

Logic Symbol

Connection Diagram

16-Pin DIP

TL/F/9892–2

TL/F/9892–1

Pin Names

Description

Count Enable Input (Active LOW)

Clock Pulse Input

Count Modulus Control Input

Asynchronous Master Set Input

ECL Outputs

Q, Q

QTTL

TTL Output

2 kX Resistor to M

REF

400X Resistor to V

1995 National Semiconductor Corporation

TL/F/9892

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6 7...10

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