®
ispLSI 1024/883
In-System Programmable High Density PLD
Functional Block Diagram
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 4000 PLD Gates
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
— 48 I/O Pins, Six Dedicated Inputs
— 144 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
D
D
D
D
Q
Q
Q
Q
Logic
Array
GLB
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 60 MHz Maximum Operating Frequency
— tpd = 20 ns Propagation Delay
Global Routing Pool (GRP)
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
CLK
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
0139-A-isp
Description
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
The ispLSI 1024/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 144 Registers,
48 Universal I/O pins, six Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1024/883
features5-Voltin-systemprogrammabilityandin-system
diagnostic capabilities. It is the first device which offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
The basic unit of logic on the ispLSI 1024/883 device is
theGenericLogicBlock(GLB).TheGLBsarelabeledA0,
A1 .. C7 (see figure 1). There are a total of 24 GLBs in the
ispLSI 1024/883 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicatedinputs. AlloftheGLBoutputsarebroughtback
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
unctional Block Diagram
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
1024MIL_01
1
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