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100354QC PDF预览

100354QC

更新时间: 2024-02-03 11:29:52
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路
页数 文件大小 规格书
9页 93K
描述
Low Power 8-Bit Register with Cut-Off Drivers

100354QC 技术参数

生命周期:Contact Manufacturer包装说明:QCCJ,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.77Is Samacsys:N
其他特性:WITH 25 OHM LINE DRIVE CAPABILITY系列:100K
JESD-30 代码:S-PQCC-J28长度:11.43 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-EMITTER WITH CUT-OFF
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):2.8 ns
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.43 mm
Base Number Matches:1

100354QC 数据手册

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October 1989  
Revised August 2000  
100354  
Low Power 8-Bit Register with Cut-Off Drivers  
reduces termination power and prevents loss of low state  
noise margin when several loads share the bus.  
General Description  
The 100354 contains eight D-type edge triggered, master/  
The 100354 outputs are designed to drive a doubly termi-  
nated 50transmission line (25load impedance). All  
inputs have 50 kpull-down resistors.  
slave flip-flops with individual inputs (Dn), true outputs (Qn),  
a clock input (CP), an output enable pin (OEN), and a com-  
mon clock enable pin (CEN). Data enters the master when  
CP is LOW and transfers to the slave when CP goes HIGH.  
When the CEN input goes HIGH it overrides all other  
inputs, disables the clock, and the Q outputs maintain the  
last state.  
Features  
Cut-off drivers  
Drives 25load  
A Q output follows its D input when the OEN pin is LOW. A  
HIGH on OEN holds the outputs in a cut-off state. The cut-  
off state is designed to be more negative than a normal  
ECL LOW level. This allows the output emitter-followers to  
turn off when the termination supply is 2.0V, presenting a  
high impedance to the data bus. This high impedance  
Low power operation  
2000V ESD protection  
Voltage compensated operating range = −4.2V to 5.7V  
Available to industrial grade temperature range  
Ordering Code:  
Order Number Package Number  
Package Description  
100354PC  
100354QC  
100354QI  
N24E  
V28A  
V28A  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
Industrial Temperature Range (40°C to +85°C)  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagrams  
24-Pin DIP  
Pin Descriptions  
Pin Names  
Description  
Data Inputs  
Clock Enable Input  
28-Pin PLCC  
D0D7  
CEN  
CP  
Clock Input (Active Rising Edge)  
Output Enable Input  
Data Outputs  
OEN  
Q0Q7  
© 2000 Fairchild Semiconductor Corporation  
DS010610  
www.fairchildsemi.com  

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