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100353 PDF预览

100353

更新时间: 2024-11-08 22:37:19
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
8页 169K
描述
Low Power 8-Bit Register

100353 数据手册

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August 1998  
100353  
Low Power 8-Bit Register  
General Description  
Features  
n Low power operation  
n 2000V ESD protection  
The 100353 contains eight D-type edge triggered, master/  
slave flip-flops with individual inputs (Dn), true outputs (Qn),  
a clock input (CP), and a common clock enable pin (CEN).  
Data enters the master when CP is LOW and transfers to the  
slave when CP goes HIGH. When the CEN input goes HIGH  
it overrides all other inputs, disables the clock, and the Q out-  
puts maintain the last state.  
=
n Voltage compensated operating range −4.2V to −5.7V  
n Available to MIL-STD-883  
The 100353 output drivers are designed to drive 50termi-  
nation to −2.0V. All inputs have 50 kpull-down resistors.  
Logic Symbol  
Pin Names  
D0–D7  
CEN  
Description  
Data Inputs  
Clock Enable Input  
Clock Input (Active Rising Edge)  
Data Outputs  
CP  
Q0–Q7  
NC  
No Connect  
DS100316-4  
© 1998 National Semiconductor Corporation  
DS100316  
www.national.com  

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