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0462-0040-02

更新时间: 2024-11-03 02:50:59
品牌 Logo 应用领域
BEL 延迟线逻辑集成电路
页数 文件大小 规格书
1页 57K
描述
5 TAP LEADING EDGE CONTROL STANDARD DELAY MODULES

0462-0040-02 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.7其他特性:MAX RISE TIME CAPTURED
系列:F输入频率最大值(fmax):31.25 MHz
JESD-30 代码:R-PSIP-T8JESD-609代码:e0
逻辑集成电路类型:ACTIVE DELAY LINE功能数量:1
抽头/阶步数:5端子数量:8
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SIP封装等效代码:SIP8,.06
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):40 mA可编程延迟线:NO
Prop。Delay @ Nom-Sup:40 ns认证状态:Not Qualified
座面最大高度:8.128 mm子类别:Delay Lines
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:SINGLE
处于峰值回流温度下的最长时间:NOT SPECIFIED总延迟标称(td):40 ns
Base Number Matches:1

0462-0040-02 数据手册

  
defining a degree of excellence  
5 TAP LEADING EDGE CONTROL  
STANDARD DELAY MODULES  
-
Cat 25 R3  
.81 Max  
.20 Max  
3
4
5
6
7
.020  
Vcc 1  
.32 Max  
.12 Min  
*
In 2  
Gnd 8  
.012  
.008  
.018  
.10 Typ  
+
.70 .01  
+
.10 .02  
(
)
bel DC  
(
)
P/N  
Part Numbers  
Test Conditions @ 25oC  
Total  
Delay  
per Tap  
Rise  
Time  
Ein  
Trin  
PW  
PP  
Iccl  
Vcc  
Pulse Voltage  
Rise Time  
Pulse Width  
Pulse Period  
Supply Current  
Supply Voltage  
3.2 Volts  
Thru-Hole  
Delay  
25 ns  
30 ns  
35 ns  
40 ns  
45 ns  
50 ns  
60 ns  
70 ns  
80 ns  
90 ns  
100 ns  
150 ns  
200 ns  
3.0 ns (10%-90%)  
1.2 x Total Delay  
4 x Pulse Width  
35 ma Typical  
5.0 Volts  
0462-0025-02  
0462-0030-02  
0462-0035-02  
0462-0040-02  
0462-0045-02  
0462-0050-02  
0462-0060-02  
0462-0070-02  
0462-0080-02  
0462-0090-02  
0462-0100-02  
0462-0150-02  
0462-0200-02  
5 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
3 ns  
6 ns  
7 ns  
8 ns  
9 ns  
10 ns  
12 ns  
14 ns  
16 ns  
18 ns  
20 ns  
30 ns  
40 ns  
Electrical Characteristics  
Min.  
4.75  
2.0  
Max. Units  
5.25  
Vcc Supply Voltage  
V
V
V
ma  
ma  
V
Vih Logic 1 Input Voltage  
Vil Logic 0 Input Voltage  
Ioh Logic 1 Output Current  
Iol Logic 0 Output Current  
Voh Logic 1 Output Voltage  
Vol Logic 0 Output voltage  
Vik Input Clamp Voltage  
Iih Logic 1 Input Current  
0.8  
-1  
20  
2.7  
-60  
0.5  
-1.2  
20  
-0.6  
-150  
25  
V
V
ua  
ma  
ma  
ma  
ma  
C
Tolerances  
Iil  
Logic 0 Input Current  
+
Ios Short Circuit Output Current  
Icch Logic 1 Supply Current  
Iccl Logic 0 Supply Current  
Ta Operating Free Air Temperature  
PW Min. Input Pulse Width of Total Delay  
Input to Taps 2 ns or 5% , Whichever is Greater  
Tap to Tap 2 ns or 7% , Whichever is Greater  
Delays measured @ 1.5 V levels on Leading Edge only  
with no loads on Taps  
Rise and Fall Times measured from 0.75 V to 2.4 V levels  
+
40  
70o  
0o  
40  
%
50  
%
d
Maximum Duty Cycle  
100 + (25000/TD) PPM/OC  
)
(
Tc Temp. Coeff. of Total Delay TD  
Drive Capabilities  
Nh Logic 1 Fanout  
Nl Logic 0 Fanout  
-
-
20 TTL Loads Max.  
10 TTL Loads Max.  
Notes  
Transfer molded for better reliability  
Compatible with TTL & DTL circuits  
Terminals: Electro-Tin plate phosphor bronze  
Other Delays and Tolerances Available  
Consult Sales  
Performance warranty is limited to specified parameters listed  
Specifications subject to change without notice.  
Corporate Office  
Bel Fuse Inc.  
Far East Office  
Bel Fuse Ltd.  
European Office  
Bel Fuse Europe Ltd.  
198 Van Vorst Street, Jersey City, NJ 07302-4496  
Tel: 201-432-0463  
Fax: 201-432-9542  
E-Mail: BelFuse@belfuse.com  
Internet: http://www.belfuse.com  
8F/8 Luk Hop Street  
San Po Kong  
Kowloon, Hong Kong  
Tel: 852-2328-5515  
Fax: 852-2352-3706  
Preston Technology Management Centre  
Marsh Lane, Preston PR1 8UD  
Lancashire, U.K.  
Tel: 44-1772-556601  
Fax: 44-1772-888366  
6

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