Using a PCI Bus as the I/O Bus on an
Am29030t Microprocessor Design
Advanced
Micro
Application Note
Devices
by David Stoenner
This application note describes how the Peripheral Component Interconnect (PCI) bus can be used
as the I/O bus portion on a two-bus microcontroller design. Additionally, one programmable logic part,
the MACHr220 device, is added for the entire control logic for both the memory control and the signal
conversion between the Am29030t microprocessor and Revision 2.0 of the PCI I/O bus.
Arbitration on the PCI bus ranges from a simple design
INTRODUCTION
of direct priority to a more complicated design of using
arbitration under the existing bus master for the nextbus
master. The protocol also supports bus master preemp-
tion if desired. Additionally, complex caching cycles for
multiprocessors also are defined. With forethought, the
PCI SIG specified that these features be optional and
not required.
The Peripheral Component Interconnect (PCI) local bus
is a high-performance, 32-bit or 64-bit bus with multi-
plexed address and data lines. It is intended for use as
an interconnect mechanism between highly integrated
peripheral controller components, peripheral add-in
boards, and processor/memory systems. Because the
bus is multiplexed, the number of pin contacts is re-
duced, making the peripheral cheaper to implement. To
accomplish this, PCI adds a layer between the CPU and
the peripherals, resulting in a processor-independent
bus that can be used for a variety of CPUs and proces-
sor speeds.
Use of the PCI Bus in this Design
This design focuses on the minimum requirements of
thePCIbus, withtheexceptionofparity. Currently, parity
is not supported on this design because of the complex-
ity of the chips that would need to be added to the de-
sign. Bus master arbitration is limited to the Am29030
processor “parked” on the PCI bus being the main mas-
ter, and the peripheral chips requesting the bus as nec-
essary. No support for time-out and bus master
preemption is included, so it is the responsibility of each
master to ensure that each peripheral does not use the
bus to the exclusion of the other peripherals.
The PCI bus is a well-defined interface that is specified
for the signals as well as the physical characteristics of
the connector and the loading. Since inexpensive pe-
ripherals will become available to meet PC needs, it
would therefore be advantageous to extend the use of
the PCI bus into the embedded processor market. Since
the 29Kt Family is one of the premiere RISC families
used in embedded control, this application note shows
how easily the PCI bus can be adapted to the 29K Fami-
ly processor to meet the requirement of an I/O bus.
The memory design is taken directly from the original
EZ-030 demonstration board (see the EZ-030 Demon-
stration Board Theory of Operation application note),
except that the MACH220 device replaces all the dis-
crete PALr devices of the EZ-030 board design. Since
the EZ-030 board supports a memory clock (MEMCLK)
of 16 MHz, this application note also focuses at 16 MHz
for both the memory and the PCI bus clock. The PCI bus
clock is defined from 0 to 33 MHz, so this falls within that
limit. Also, 33-MHz clock rates, and therefore the bus,
require more careful layout than the 16-MHz clock.
THE PCI BUS
In order to create an industry standard for PCI, the PCI
Special Interest Group (SIG) has defined a specifica-
tion. The PCI Local Bus Specification, Revision 2.0, de-
fines the protocol, electrical, mechanical, and
configuration specifications for PCI local bus compo-
nents and expansion boards. (See page 5 for informa-
tion on ordering the specification.)
The rest of this application note focuses on the
MACH220 device and the extra circuitry needed to im-
plement the control portion of the PCI bus. Schematics
for this design are shown in Appendix A and the PAL
equations are listed in Appendix B.
Basics of the PCI Bus
The PCI bus is an address/data multiplexed bus. Addi-
tionally, the control signals are multiplexed with the byte
control signals. The PCI bus supports a burst protocol
that accepts an address with multiple data packets. This
protocol is identical to the 29K Family, making the inter-
face design easily accomplished.
Publication# 18468 Rev. A Amendment /0
Issue Date: May 1994
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