Datasheet > PTN3700EV/G

PTN3700EV/G

更新时间： 2025-07-14 19:53:39

品牌	Logo	应用领域
恩智浦 - NXP		商用集成电路
页数	文件大小	规格书
43页	281K
描述
IC SPECIALTY CONSUMER CIRCUIT, PBGA56, 4 X 4.50 MM, 0.65 MM HEIGHT, LEAD FREE, PLASTIC, SOT991-1, VFBGA-56, Consumer IC:Other

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PTN3700EV/G 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	VFBGA,	针数：	56
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.6	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PBGA-B56	长度：	4.5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	56	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1 mm
最大供电电压 (Vsup)：	1.95 V	最小供电电压 (Vsup)：	1.65 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	0.5 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	4 mm	Base Number Matches：	1

PTN3700EV/G 数据手册

PTN3700

1.8 V simple mobile interface link bridge IC

Rev. 3 — 12 October 2011

Product data sheet

1. General description

The PTN3700 is a 1.8 V simple mobile interface link bridge IC which can function both as

a transmitter-serializer or a receiver-deserializer for RGB888 video data. When configured

as transmitter (using input pin TX/RX), the PTN3700 serializes parallel CMOS video input

data into 1, 2 or 3 subLVDS-based high-speed serial data channels. When configured as

receiver, the PTN3700 deserializes up to 3 high-speed serial data channels into parallel

CMOS video data signals.

The parallel interface of the PTN3700 is based on the conventional and widely used 24-bit

wide data bus for RGB video data, plus active LOW HS (Horizontal Synchronization) and

VS (Vertical Synchronization) signals, and an active HIGH DE (Data Enable) signal. An

additional two auxiliary bits A[1:0] are provided to permit signaling of miscellaneous status

or mode information across the link to the display. The serial interface link of the PTN3700

is based on the open Simple Mobile Interface Link (SMILi) definition. In order to keep

power low while accommodating various display sizes (e.g., up to 24-bit, 60 frames per

second XVGA), the number of high-speed serial channels (‘lanes’) is configurable from

1 to 3 depending on the bandwidth needed. The data link speed is determined by the

PCLK (Pixel Clock) rate and the number of serial channels selected.

In order to maintain a low power profile, the PTN3700 has three power modes,

determined by detection of an active input clock and by shutdown pin XSD. In Shutdown

mode (XSD = LOW), the PTN3700 is completely inactive and consumes a minimum of

current. In Standby mode (XSD = HIGH), the device is ready to switch to Active mode as

soon as an active input clock signal is detected, and assume normal link operation.

In Transmitter mode, the PTN3700 performs parity calculation on the input data (R[7:0],

G[7:0], B[7:0] plus HS, VS and DE data bits) and adds an odd parity bit CP to the serial

transmitted data stream. The PTN3700 in Receiver mode also integrates a parity

checking function, which checks for odd parity across the decoded input word (R[7:0],

G[7:0], B[7:0] plus HS, VS and DE data bits), and indicates whether a parity error has

occurred on its CPO out pin (active HIGH). When a parity error occurs, the most recent

error-free pixel data will be output instead of the received invalid pixel data.

PTN3700 in Receiver mode offers an optional advanced frame mixing feature, which

allows 18-bit displays to effectively display 24-bit color resolution by applying a

patent-pending pixel data processing algorithm to the 24-bit video input data.

One of two serial transmission methods is selectable: pseudo source synchronous

transmission based on the pixel clock, or true source synchronous transmission based on

the bit clock. The latter uses a patent-pending methodology characterized by zero

overhead and operation guaranteed free from false pixel synchronization.

12 3 4 5 6 7...43

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